Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
Install
The individual skill folder is not confirmed. This command opens the repository’s skill selector; follow the upstream instructions.
skills CLI
npx skills add Eriemon/verilog-generator