Use when creating, writing, reviewing, annotating, repairing, refactoring, or validating readable Verilog RTL, including synthesizable Verilog-2001 .v files, existing-RTL analysis, semantic comment annotation, testbench scaffold planning, ASIC-quality review, local or remote Vivado/xsim validation, evidence-backed repair, and workflow trace diagnosis.
安装
尚未确认此技能的独立目录。下面命令会打开仓库技能选择器，请按上游说明选择技能。
skills CLI
npx skills add Eriemon/verilog-generator